- Google (Portland, OR)
- …. + Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing microarchitecture and RTL design ... 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or...languages such as Verilog or SystemVerilog. + Experience with RTL language (eg SystemVerilog) and related design processes (eg,… more