- Meta (Austin, TX)
- …Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...equivalent practical experience. 9. 5+ years of experience in static verification tools 10. Experience with Lint, Clock Domain… more
- SpaceX (Irvine, CA)
- SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... enabling human life on Mars. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) At SpaceX we're leveraging our experience in… more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...analysis , SI noise analysis 13. Experience with running Static Timing Analysis for full chip using DMSA 14.… more
- SpaceX (Redmond, WA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC… more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- Meta (Austin, TX)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... of complex digital top level and/or blocks, with experience across the complete ASIC /SOC design flow including routing, static timing closure, EM/IR analysis and… more
- NVIDIA (Westford, MA)
- …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering ... area targets. + Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking,...path planning and crafting needed. + Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus.… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... timing convergence, timing constraints generation and management, and ECO generation and implementation . What we need to see: + BS (or equivalent experience) in… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... timing constraints, driving timing and power convergence, as well as ECO implementation + Apply knowledge and experience to improve timing convergence flows working… more