• ASIC Package SI / PI

    Capgemini (San Francisco, CA)
    …US by Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _ASIC Package SI / PI Engineer_ **Location:** _CA-San Francisco_ **Requisition ... **Job description:** Capgemini Engineering is looking for an experience ASIC Package Engineer to join our semiconductor..., and PCB Design teams to design and ensure package /system SI / PI performance meets expectation… more
    Capgemini (03/19/25)
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  • ASIC Package Engineer SI

    Meta (Sunnyvale, CA)
    …based on 2.5D/3D package technology 2. Drive package level Lead ASIC package SI / PI design activities, including substrate stackup/material ... **Summary:** Meta is looking for an experienced ASIC Packaging Engineer, Signal Integrity, and...as part of a world-class engineering team. **Required Skills:** ASIC Package Engineer SI / PI more
    Meta (02/14/25)
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  • Physical Design Engineer - ASIC

    Capgemini (San Francisco, CA)
    …Capgemini. **Job:** _Developer_ **Organization:** _ERD PPL US_ **Title:** _Physical Design Engineer - ASIC Package Engineer SI / PI Engineer_ **Location:** ... **Job description:** Experienced ASIC Packaging Engineer, Signal Integrity, and..., and PCB Design teams to design and ensure package /system SI / PI performance meets expectation… more
    Capgemini (03/13/25)
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  • Sr. Hardware System Design Engineer

    Broadcom (San Jose, CA)
    …interfaces, and other critical components. + Collaborate closely with cross-functional teams, including ASIC , SI , PI , DVT, Sysops, Software, AE, and ... equity award agreements. Broadcom offers a competitive and comprehensive benefits package : Medical, dental and vision plans, 401(K) participation including company… more
    Broadcom (02/01/25)
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  • Senior Signal Integrity Engineer (Hardware)

    Palo Alto Networks (Santa Clara, CA)
    …and optimize design performance / risk / cost / manufacturability + Contribute to ASIC package design for SI + Model complex 3-dimensional structures ... designs + Model and analyze power delivery networks for ASIC / package /module and PCB + Create SI...Power integrity design and analysis and well versed in PI simulation tool such as PowerSI/DC, etc. + Working… more
    Palo Alto Networks (03/29/25)
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  • ASIC Package Signal/Power Integrity…

    Cisco (San Jose, CA)
    …or related field * Experience with MATLAB or Python scripting * Experience with SI / PI of 2.5D advanced ASIC packaging * Experience with Raptor-X * ... Power Integrity to help us develop our next generation ASIC packaging . You will work on cutting-edge...design rules for ultra-high speed signaling * Analyze substrate SI / PI and provide feedback for layout *… more
    Cisco (04/02/25)
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  • Lead Advanced Microelectronics Packaging

    The Boeing Company (El Segundo, CA)
    …engineering, foundry, test, and QA + Create and execute substrate breakout patterns for ASIC packaging + Optimize package pinouts by evaluating system-level ... has an exciting opportunity as a **Lead Advanced Microelectronics Packaging Design Engineer** . Come join us as part...for flipchip, wirebond, and MCM packages + SI / PI tools (XtractIM, PowerSI, HFSS, Q3D, etc.), package more
    The Boeing Company (03/30/25)
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  • Silicon Packaging Design Engineer

    Meta (Sunnyvale, CA)
    …Xpedition platform tools. 10. Basic understanding in one of the SI / PI tools (XtractIM, PowerSI, HFSS, Q3D, etc.), package model extraction, S-parameters ... custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal for our ASIC...part of a world-class engineering team. **Required Skills:** Silicon Packaging Design Engineer Responsibilities: 1. Perform package more
    Meta (01/17/25)
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  • Senior Engineer, Package Design

    MetaOption, LLC (Milpitas, CA)
    …need a Sr. candidate 7 + years of experience in Package design, with a mix of Si and Pi . Someone that has held a position of ownership on multiple levels of ... ASIC Package Design on next generation chips....PCIeX5 and 6, LPDDR4,5, Ethernet 25 GBps, power aware SI / PI analysis, up to 40 GHZ s-parameters… more
    MetaOption, LLC (03/17/25)
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  • Master Engineer

    Broadcom (Irvine, CA)
    …2.5D & Co-Packaged Optics (5nm, 3nm and beyond) Work with IC design, system design, package SI / PI & thermal engineering teams to design custom packages using ... plan & IP bump pattern design and optimization for package design requirements (eg layer-count, stack-up, escape architecture, BGA...Cadence APD Ensure designed packages meet CPI, SI / PI , and stringent thermal requirements (1000W+) of… more
    Broadcom (03/29/25)
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