• ASIC Timing and Methodology

    Qualcomm (San Diego, CA)
    …Inc. **Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** As a Timing Engineer , you will play a vital role in Timing ... and Tempus. + You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus and best in...for STA timing sign off. + A timing Engineer should be able to understand… more
    Qualcomm (01/14/25)
    - Related Jobs
  • ASIC Engineer , Methodology

    Meta (Austin, TX)
    …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Methodology Responsibilities: 1. Work with our ... **Summary:** Meta is hiring ASIC Methodology Engineers within our Infrastructure... signoff automation and test structures to ensure Meta's timing methodology is A0-production ready. 5. Drive… more
    Meta (02/13/25)
    - Related Jobs
  • ASIC Implementation Engineer

    Meta (Sunnyvale, CA)
    …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....Timing , Area, Power. 6. Developing Automation scripts and Methodology for all FE-tools including ( Synthesis, STA). 7.… more
    Meta (01/23/25)
    - Related Jobs
  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... as ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
    NVIDIA (03/18/25)
    - Related Jobs
  • Senior High-Performance ASIC Timing

    NVIDIA (Santa Clara, CA)
    …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... human inventiveness and intelligence. What you'll be doing: + Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU,… more
    NVIDIA (03/25/25)
    - Related Jobs
  • ASIC Design Technical Leader - Design…

    Cisco (San Jose, CA)
    …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
    Cisco (04/01/25)
    - Related Jobs
  • ASIC Design Engineer , Senior…

    Cisco (San Jose, CA)
    …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...customer shipments. Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
    Cisco (02/20/25)
    - Related Jobs
  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention ... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's...be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into… more
    NVIDIA (03/20/25)
    - Related Jobs
  • ASIC Package Engineer SI/PI

    Meta (Sunnyvale, CA)
    **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its ASIC packaging team to support ... can create as part of a world-class engineering team. **Required Skills:** ASIC Package Engineer SI/PI Responsibilities: 1. Drive chip-package-system co-design… more
    Meta (02/14/25)
    - Related Jobs
  • ASIC Implementation Engineer

    Meta (Sunnyvale, CA)
    …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....optimization techniques and generate optimized Gate Level Netlist for Timing , Area, Power. 2. Debug the timing /area/congestion… more
    Meta (03/06/25)
    - Related Jobs