• High - Speed IO

    NVIDIA (Santa Clara, CA)
    … to be part of a Silicon Hardware team. You will dive into next-gen high speed interconnects like NVLink and NVLink-C2C to make advancements in efficiency and ... with Hardware. + Strong EE fundamentals, knowledgeable in computer architecture, high speed interfaces, timing analysis, process variations, statistical error… more
    NVIDIA (03/15/25)
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  • Serdes / High Speed IO DFT…

    Broadcom (Mendota Heights, MN)
    …please Sign-In before you apply.** **Job Description:** SerDes DFT & Test Engineer Broadcom's ASIC Product Division is seeking candidates for SerDes Verification & ... Test Engineer position at our Fort Collins Development Center in Colorado. In this role, you will play a crucial part in ensuring the robustness and reliability of… more
    Broadcom (01/16/25)
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  • Principal Engineer - Signal and Power…

    Qualcomm (Folsom, CA)
    …and presentation of results. This candidate's main functional area is high - speed SerDes/memory interface electrical model extraction and system-level simulation, ... smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital and/or analog),...and document IP (block/SoC) development for a variety of high performance, high quality, low power world… more
    Qualcomm (02/21/25)
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  • Principal RF Engineer / Sr. Principal RF…

    Northrop Grumman (Linthicum, MD)
    …utilizing test instrumentation such and power supplies, network analyzers, Oscilloscopes, spectrum analyzers, High speed digital IO + Ability to obtain and ... position will be filled at either the Principal RF Engineer or Sr. Principal RF Engineer level...such and power supplies, network analyzers, Oscilloscopes, spectrum analyzers, High speed digital IO +… more
    Northrop Grumman (03/07/25)
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  • ASIC Package Engineer SI/PI

    Meta (Sunnyvale, CA)
    …and develop detailed engineering test plans 5. Conduct post Si validation and qualification of high speed interface for ASICs 6. Validate high speed ... **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its...15. Expertise in signal and power integrity for various high speed interconnects (eg, HBMx, D2D, Ethernet,… more
    Meta (02/14/25)
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  • Physical Design Engineer - ASIC Package…

    Capgemini (San Francisco, CA)
    …SIPI. *Develop SIPI validation methodology and develop detailed engineering test plans *Validate high speed interface and PDN impedance in lab to correlate ... **Job description:** Experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for...pre-layout and post-layout simulation flow with a focus on high - speed interface and PDN, create simulation models… more
    Capgemini (03/13/25)
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  • IP Integration Lead Engineer

    Broadcom (Fort Collins, CO)
    …with analog and physical composition teams to optimize the size and power delivery to high IO density PHYs + Work with teams to analyze power integrity (droop, ... of related experience + Understanding of design trade offs for power, area, and speed in ASIC designs. + Understanding of complex issues related to timing closure,… more
    Broadcom (03/11/25)
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  • Silicon Validation Engineer , Reality Labs

    Meta (Sunnyvale, CA)
    high - speed protocols (ie, MIPI, PCIe, USB, DDR) and hands-on experience in high - speed IO bring-up. 13. Expertise with using lab equipment, such as ... high performance silicon and leading the effort to ensure high -quality silicon delivery. **Required Skills:** Silicon Validation Engineer , Reality Labs… more
    Meta (03/15/25)
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  • Field Application Engineer AMD/Xilinx

    Avnet (Columbia, MD)
    …or equivalent + 3-5+ years experience FPGA-based architecture definition, design, and support ( High Speed Serial IO , Embedded Processor, or DSP knowledge ... **Job Summary:** As the AMD Xilinx dedicated Field Application Engineer you will be a key member of a...for FPGA's & SoC's including power distribution & dissipation, high speed interface design, and debug. +… more
    Avnet (01/26/25)
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  • Senior Mask Design Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …silicon chips in mass production. + Knowledge of high performance analog and high speed IO layout techniques such as common centroid layout, matching, ... We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing...and implement IC physical layout for mixed-signal functions like high speed SerDes, Analog to Digital &… more
    NVIDIA (03/06/25)
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