- SpaceX (Bastrop, TX)
- IC Packaging Engineer , Silicon Technology (Starlink) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring ... make this possible, with the ultimate goal of enabling human life on Mars. IC PACKAGING ENGINEER , SILICON TECHNOLOGY (STARLINK) SpaceX is leveraging its… more
- SpaceX (Bastrop, TX)
- Principal IC Packaging Engineer , Silicon Technology (Starlink) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL IC PACKAGING ENGINEER , SILICON TECHNOLOGY (STARLINK) SpaceX is leveraging its… more
- SpaceX (Bastrop, TX)
- Sr. IC Packaging Test Engineer , Silicon Technology (Starlink) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. IC PACKAGING TEST ENGINEER , SILICON TECHNOLOGY (STARLINK) SpaceX is leveraging its experience in… more
- SpaceX (Bastrop, TX)
- IC Packaging Test Engineer , Silicon Technology (Starlink) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. IC PACKAGING TEST ENGINEER , SILICON TECHNOLOGY (STARLINK) Starlink believes in providing fast, reliable… more
- SpaceX (Irvine, CA)
- IC Layout Engineer ( Silicon ...power and ground distribution as well as working with packaging engineer to determine pad locations + ... this possible, with the ultimate goal of enabling human life on Mars. IC LAYOUT ENGINEER ( SILICON ENGINEERING) At SpaceX we're leveraging our experience in… more
- Google (Fremont, CA)
- …burn-in hardware for backplane (CMOS) ICs. + Work with external vendors to design custom IC packaging and hardware for ESD and latch-up testing. + Lead failure ... practical experience. + 4 years of experience in semiconductor IC reliability, or 3 years of experience with an...commonly used tools like JMP, Reliasoft, etc. As a Silicon Reliability Engineer , you will be responsible… more
- MIT Lincoln Laboratory (Lexington, MA)
- …lithographic mask layout, material growth and characterization, fabrication (eg, silicon , compound-semiconductor, wafer bonding, flip-chip hybrid), packaging , ... growth, charge-coupled device (CCD) imagers, 193-nm lithography, fully depleted silicon -on-insulator (FDSOI) CMOS electronics, semiconductor diode lasers and amplifiers,… more
- The Boeing Company (El Segundo, CA)
- …in multi-functional discussions for package architecture and technology roadmap (partner with Silicon IC team to optimize chip Floorplan and bump placement). ... has an exciting opportunity as a **Lead Advanced Microelectronics Packaging Design Engineer ** . Come join us...Designing and optimizing layout for advanced substrates of HDI IC substrate, Silicon , or LTCC substrates, considering… more
- Cisco (San Jose, CA)
- …or if a sufficient number of applications are received. Who We Are Cisco Silicon One is a business organization building and selling ASICs inside and outside of ... Cisco. We have a long track record of building large, high-performance Silicon ASICs for Cisco's internal platforms and external customers. We are a specialized ASIC… more
- Broadcom (Irvine, CA)
- …including bump cell definition (metal scheme, geometry, metallurgy etc.) Manage IC packaging activity from concept through development, qualification through ... (eg 224G PAM4, 112GPAM4, HBM2e/3) for new advanced node silicon (7nm, 5nm, 3nm..) chip floor plan & IP...integrity [PI] requirements) Work with business unit marketing and IC design teams to select the optimum package solution… more