- Qualcomm (San Diego, CA)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Cisco (San Jose, CA)
- …or MS Degree in Electrical or Computer Engineering with 10 Years Experience with ASIC design timing closure flow ( STA ) and methodology. * Hands-on experience ... timing and routing congestion issues, influencing key design and physical implementation decisions early in...constraints generation and validation, clock domain crossing checks, and timing closure. * Expertise in STA tools… more
- Cadence Design Systems, Inc. (Cary, NC)
- …physical design implementation , including floor planning, power grid design , place and route, clock tree synthesis, timing closure, power/signal ... of challenging designs, ie low power and high speed design . As well as participating in or leading next...LVS, ANT, ERC etc. - Deep experience of static timing analysis - Ability to learn quickly - High… more
- SpaceX (Irvine, CA)
- …to meet critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA / Timing Engineer/Level I: $120,000.00 - $145,000.00/per year ... SOC/ASIC Timing Signoff & Front-End Implementation Engineer...Physical Design STA / Timing Engineer/Level II: $140,000.00 - $170,000.00/per year… more
- SpaceX (Irvine, CA)
- …in advanced nodes + Experience with test modes, mode merging to optimize physical design implementation and STA Signoff. + Experience with power intent ... Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer...will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In… more
- Qualcomm (Folsom, CA)
- …you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ... Design Timing Engineer,... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC, Innovous… more
- Meta (Austin, TX)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints ... scripts and Methodology for all FE-tools including ( Synthesis, STA ). 7. Work closely with the Design ...them with the handoff tasks. 8. Interact with Physical Design Engineers and provide them with timing /congestion… more
- NVIDIA (Westford, MA)
- …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon ... you will be doing: + You will drive physical design and timing of high-frequency and low-power...including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation .… more
- Meta (Austin, TX)
- …RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the ... Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 10. Work closely with the Design...them with the handoff tasks. 11. Interact with Physical Design Engineers and provide them with timing /congestion… more
- Cadence Design Systems, Inc. (AL)
- …Systems Inc. (https://www.cadence.com/) is looking for a motivated Principal Solutions Engineer: Physical Design - Implementation and Signoff to work with us in ... Brazil. As a Principal Solutions Engineer: Physical Design - Implementation and Signoff, you will...digital SoC IPs for customer technical needs; + Perform STA to ensure timing closure; + Perform… more