- Qualcomm (San Diego, CA)
- … ASIC engineers with excellent analytical and technical skills, and a focus on low power , high performance ASIC designs, and, ability to execute critical ... low power designs. + Strong knowledge in the entire low power , high performance ASIC /SoC design flows (micro-architecture, RTL design, verification,… more
- Meta (Austin, TX)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Power Responsibilities: 1. Work with Architecture and ... **Summary:** Meta is hiring ASIC Power Engineers within our Infrastructure...abstraction: C-model, RTL, Gate, Layout. 6. Optimize design for low - power with the understanding of system level… more
- Meta (Denver, CO)
- …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Power Responsibilities: 1. Work with Architecture and ... **Summary:** Meta is hiring ASIC Power Engineers within our Infrastructure...abstraction: C-model, RTL, Gate, Layout 6. Optimize design for low - power with the understanding of system level… more
- SpaceX (Irvine, CA)
- … power intent verification and post synthesis timing validation flows + Execute low power design and physical synthesis, deploying knowledge of unified ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer...flow, top-down and bottom-up design methodologies + Knowledge of low - power methodologies and leakage/dynamic power … more
- Amazon (Austin, TX)
- Description Amazon Web Services provides a highly reliable, scalable, low -cost infrastructure platform in the cloud that powers hundreds of thousands of businesses ... rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies...ownership and deliveries * 3+ years of experience with power analysis and optimization * Experience working with SOC… more
- Meta (Austin, TX)
- …for individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip ... (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop...and power grid planning. 18. Experience with low power implementation, power gating,… more
- Meta (Austin, TX)
- …for individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip ... (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop...and power grid planning. 19. Experience with low power implementation, power gating,… more
- Capgemini (San Francisco, CA)
- …complex designs - 1M instances and clock frequencies about 1 GHz *Experience with low power implementation and signoff, power gating, multiple voltage rails, ... **Physical Design Engineer ** **Job Description:** **The ASIC Physical...Responsibility:** *Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO… more
- Meta (Austin, TX)
- …Memories. 22. Knowledge of STA signoff and understanding of AOCV, POCV 23. Experience with low power techniques for reducing power . 24. Experience with EDA ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
- Amazon (San Diego, CA)
- …implementation. * Experience in leading physical design. * Strong exposure to UPF flow for low power design. * Strong written and verbal skills * Experience of ... Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low...flow for various technology nodes. * Work with the ASIC design and DFT teams to understand the design… more