- SpaceX (Irvine, CA)
- Sr. SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING)… more
- SpaceX (Irvine, CA)
- SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... this possible, with the ultimate goal of enabling human life on Mars. SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)… more
- SpaceX (Redmond, WA)
- …flow development experience in industry PREFERRED SKILLS AND EXPERIENCE: + Strong experience in ASIC / SOC RTL2GDSII physical design and signoff flows + Strong ... Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering)...solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis… more
- Meta (Austin, TX)
- … Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC . 8. Analyze the inter-block timing and come up with IO budgets ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....Timing /physical libraries, SRAM Memories. 22. Knowledge of STA signoff and understanding of AOCV, POCV 23. Experience with… more
- Meta (Austin, TX)
- …tools 10. Experience with Lint, Clock Domain & Reset Domain crossing. 11. Experience with SOC CDC signoff 12. Knowledge of SOC Integration (Clocking, Reset, ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip… more
- Capgemini (San Francisco, CA)
- …digital top level and/or blocks, with experience across the complete ASIC / SOC design flow including routing, static timing closure, EM/IR analysis and ... **Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for...knowledge. *Experience in Block-level and Full-chip integration. *Knowledge of signoff closure - Timing with SI and… more
- Qualcomm (San Diego, CA)
- …and integrate HM constraints into SoC and ensure correlation between HM and SoC timing . + Analyze timing across modes and corners, understand concepts ... for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate...validate clock domain crossing and design constraints to achieve timing closure of complex SoC cores. +… more
- Cisco (San Jose, CA)
- …bump and rdl planning, power grid design to clock planning , routing, and timing closure. * Perform full chip DRC/LVS/ERC/ANT checks, review and debug the issues, ... provide solutions and ensure signoff clean results. * Work closely with block and...Science, with 10+ year minimum of hands-on experience in ASIC implementation and Physical verification * Experience in deep… more