- US Tech Solutions (Longmont, CO)
- …Attention to the detail. Very good communication skills (both written and verbal). Fast learner and self-starter. Need to execute our custom regression ... scripts/quality checks for our complex designs (Multimode, multimillion gates and multiple partitions). Understand the PT/DC checks and review the reports to help clean up in order to meet each milestone targets. Summarize the regression results periodically… more
- Northrop Grumman (Linthicum, MD)
- …DoD Top Secret Clearance or higher with SAP Access.** **Basic Qualifications for a Senior Principal ASIC DFT Engineer :** **Bachelor's degree with 8 years ... Grumman Mission Systems, Digital Technologies Group, is seeking an ASIC DFT Engineer to join our team...Tcl, Python or Perl.** **Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus.** **Effective communication… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... of complex digital top level and/or blocks, with experience across the complete ASIC /SOC design flow including routing, static timing closure, EM/IR analysis and… more
- Cisco (San Jose, CA)
- …provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography ... culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact * Write micro-architecture specifications and participate… more
- SpaceX (Redmond, WA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Redmond, WA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $160,000.00 - $220,000.00/per year Your actual… more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking ... + Experience in critical path planning and crafting needed. + Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus. + Solid experience in… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... project execution and/or flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and… more
- Cisco (San Jose, CA)
- …*Prior experience using Synthesis Tools: Synopsys DC/DCG/FC. *Prior experience in Static Timing Analysis & ECO: Synopsys Primetime/Cadence Tempus. *Prior experience ... with scripting such as TCL, Perl, or Python. Preferred Qualifications *Master's degree in electrical or computer engineering (or other equivalent field) with 4+ years of related work experience. *Experience using: Synopsys PTPX/Tweaker/PrimeClosure *Experience… more
- L3Harris (Camden, NJ)
- Job Title: Senior Electrical Engineer (FPGA Design) Job Code: 19447 Job Location: Camden, NJ Schedule: 9/80 Regular with every other Friday off Job Description: ... Reporting to the Manager, Engineering ( ASIC /FPGA), the Senior Member of Engineering Staff...simulations + Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA) + Perform RTL quality using:… more