- Cisco (San Jose, CA)
- …and noise, while managing ECO tasks. *Your role may include extraction and STA flow development, convergence strategies, and correlation between PNR, Spice, and ... STA , along with advising the Physical Design team on...*Additionally, you'll develop methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive… more
- SpaceX (Irvine, CA)
- …critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual ... Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer...years of experience working as a synthesis and/or front-end STA engineer PREFERRED SKILLS AND EXPERIENCE: +… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... _Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - ASIC Physical Design Engineer_ **Location:** _CA-San Francisco_… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Northrop Grumman (Baltimore, MD)
- …to join our team as a Principal Digital Engineer / Senior Principal Digital Engineer (FPGA and ASIC Design) based out of Linthicum, MD. **What You'll get ... team in Mission Systems that encompasses Digital Engineering to support FPGA and ASIC product development. + Work closely with design engineers and will utilize your… more
- SpaceX (Redmond, WA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Redmond, WA SpaceX was founded under the belief that a future where humanity is out ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $160,000.00 - $220,000.00/per year Your actual… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Westford, MA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking ... Cadence Tempus. + Solid experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- Broadcom (Fort Collins, CO)
- …** Senior Custom ASIC Engineering Lead** Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas ... such as physical design, STA , DFT, and packaging? Have you taped out so... ASIC products division is looking for a senior engineer to guide Customer teams designing… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...Electrical or Computer Engineering with 3 years' experience in ASIC Design and Timing. + Good understanding of modeling… more