- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
- NVIDIA (Westford, MA)
- …life's work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at...from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and… more
- US Tech Solutions (Longmont, CO)
- …with EDA tools that enable RTL quality checks Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to ... multitask, ramp up quickly on new flows/tools/ideas Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable **EDUCATION:** Bachelor's degree required **About US Tech Solutions:** US Tech… more
- SpaceX (Irvine, CA)
- Sr. SOC/ ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... enabling human life on Mars. SR. SOC/ ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON...COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our ... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's...be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into… more
- Northrop Grumman (Linthicum, MD)
- …DoD Top Secret Clearance or higher with SAP Access.** **Basic Qualifications for a Senior Principal ASIC DFT Engineer :** **Bachelor's degree with 8 years ... Grumman Mission Systems, Digital Technologies Group, is seeking an ASIC DFT Engineer to join our team...Python or Perl.** **Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus.** **Effective communication and… more
- RTX Corporation (Cedar Rapids, IA)
- …their needs for tomorrow. Are you up for the challenge? Join our mission today. Senior Electrical Engineer - ASIC /FPGA - Advanced Technology (Onsite) This ... position is for a motivated Senior Electrical or Computer engineering candidate to be involved...Technologies team. What You Will Do: + Requirements capture, ASIC / FPGA digital architecture and design using RTL,… more
- Capgemini (San Francisco, CA)
- **Physical Design Engineer ** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip ... of complex digital top level and/or blocks, with experience across the complete ASIC /SOC design flow including routing, static timing closure, EM/IR analysis and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer ! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the ... Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan...timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical… more
- Cisco (San Jose, CA)
- …provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography ... breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact * Write micro-architecture...participate in reviews. * Implement Verilog RTL to meet timing , performance, and power requirements. * Contribute to full… more