- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
- NVIDIA (Westford, MA)
- …life's work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and SoCs at...from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and… more
- NVIDIA (Santa Clara, CA)
- …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... intelligence. What you'll be doing: + Develop and execute timing closure plans for NVIDIA's next generation of high-performance...for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You… more
- The Boeing Company (Huntington Beach, CA)
- …opportunity for multiple ** ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal)** to join us as part of our Boeing Electronic Products ... Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products...team and third-party IP as needed + Perform static timing analysis, LEC, CDC, linting, and other necessary checks… more
- The Boeing Company (Kent, WA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC /FPGA Engineer on the Boeing Electronic Products team you will lead ... & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers at Lead,... and/or FPGA Design and Verification Engineers at Lead, Senior & Principal levels to join us as part… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our ... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's...be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...customer shipments. Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
- Palo Alto Networks (Santa Clara, CA)
- …to create an environment where we all win with precision. **Your Career** As a Design engineer on the ASIC team, you will create complex digital logic for our ... goals for area, timing , power, and testability in close collaboration with ASIC physical design engineers + Perform synthesis + Optimize floorplan + Analyze and… more
- Actalent (Anaheim, CA)
- …placement, routing, layout, and timing . + 20+ years of experience in leading senior ASIC teams and hands-on detailed ASIC engineering to successfully ... Job Title: Senior Scientist in Hardware and ASIC ...and experience in military GPS and Position Navigation and Timing (PNT) technology or other RF hardware designs. Responsibilities… more
- Cisco (San Jose, CA)
- …provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography ... breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact * Write micro-architecture...participate in reviews. * Implement Verilog RTL to meet timing , performance, and power requirements. * Contribute to full… more