• Senior CPU Implementation

    NVIDIA (Santa Clara, CA)
    We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you ... dynamic team Ways to stand out from the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl, Python, Tcl, Make… more
    NVIDIA (03/21/25)
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  • Senior Physical Design Methodology

    NVIDIA (Santa Clara, CA)
    …intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on PPA (Power, ... closure + Work with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all our product lines… more
    NVIDIA (02/20/25)
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  • Senior SoC Power Architect, Silicon

    Google (Mountain View, CA)
    …and power analysis. + 8 years of experience in SoC power management or low power design/ methodology . + Experience in CPU power in mobile SoCs from CPU ... + 5 years of experience in SoC power management or low power design/ methodology . + Experience with Application-Specific Integrated Circuit (ASIC) low power flows and… more
    Google (03/22/25)
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  • Senior Staff Data Engineer - Hybrid

    The Hartford (Columbus, OH)
    …and Performed Dynamic data Masking. + Have a solid understanding of delivery methodology (SDLC) and lead teams in the implementation of the solution according ... IT team supporting Global specialty is seeking a hands-on Senior Staff Data Engineer to enhance and support its...Experience in Performance Tuning of Jobs to reduce the CPU time/load timing. + Deeper Knowledge on SnowFlake License… more
    The Hartford (03/05/25)
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  • Senior High-Performance ASIC Timing…

    NVIDIA (Santa Clara, CA)
    …execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU , GPU and SOC designs. + Owning static timing analysis and convergence of ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and timing methodologies. + Finding the right tradeoffs and balance… more
    NVIDIA (03/25/25)
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  • Sr. Staff Design Engineer (Low Power)

    Qualcomm (Santa Clara, CA)
    …IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/ Implementation , power estimates, power analysis tools and ... IPs. Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/ Implementation , power estimates, power analysis tools and… more
    Qualcomm (04/09/25)
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  • Staff Engineer - Electrical and Computing System

    SLAC National Accelerator Laboratory (Menlo Park, CA)
    …open for designing the laboratory and operating the testing laboratory with senior scientists and collaborators from different companies. As a Computing Systems ... of both small-scale and large-scale algorithms running on different computing systems ( CPU , GPU, ASIC, FPGA etc). These may include assessing the computing… more
    SLAC National Accelerator Laboratory (03/04/25)
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  • Science and Engineering Associate - Electrical…

    SLAC National Accelerator Laboratory (Menlo Park, CA)
    …open for designing the laboratory and operating the testing laboratory with senior scientists and collaborators from different companies. As a Computing Systems ... of both small-scale and large-scale algorithms running on different computing systems ( CPU , GPU, ASIC, FPGA etc). These may include assessing the computing… more
    SLAC National Accelerator Laboratory (03/04/25)
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