- NVIDIA (Santa Clara, CA)
- …What you'll be doing: + You will be part of NVIDIA's RTL analysis CAD team, responsible for developing flows, methodology , and application support for Clock ... part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the RTL CDC...deploy, and support state-of-the-art EDA tools and methodologies for RTL analysis . + Serve as an in-house… more
- NVIDIA (Santa Clara, CA)
- …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
- Northrop Grumman (Linthicum Heights, MD)
- …UVM + Experience developing testplans, participating in reviews, test development and RTL debug ** Senior Principal Engineer Basic Qualifications:** + Bachelor's ... for you to join our team as a Principal Digital Verification Engineer/ Senior Principal Digital Verification Engineer based out of Linthicum, MD or Morrisville,… more
- Intel Corporation (Hillsboro, OR)
- …of the role include, but not limited to: + Help define DFx Scan design methodology and uarch to ensure good coverage [Scan and functional] for IP and meet products' ... ATPG tools, generate ATPG patterns via Mentor Graphic Tessent, RTL and GLS test validation to ensure quality design,...DFX arch introduce to the IP. + Perform yield analysis improvement and assisting the silicon debug + Analyze… more
- The Boeing Company (Huntington Beach, CA)
- …SiGe. SSED uses external wafer fabrication but performs design (architecture, RTL , synthesis, circuits, physical design, verification, packaging and test) in house. ... We are seeking a **Digital Integrated Circuit Design Engineer (Mid-Level, Senior or Lead)** with experience developing complex, high-performance ASICs, FPGAs, and… more
- Cisco (San Jose, CA)
- …fullchip timing in multiple timing modes. * Option to also do block level RTL design or block or top-level IP integration. * Helping develop efficient methodology ... back to block level. * Helping develop and apply methodology to ensure correctness and quality of SDCs as...block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development. * Leading the… more
- NVIDIA (Santa Clara, CA)
- …In-silicon measurement, Reset and Boot controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + ... We are now looking for a Senior ASIC Design Engineer to join our System...design concepts and experience in ASIC design flow including RTL design, verification, logic synthesis and timing analysis… more
- Northrop Grumman (Linthicum Heights, MD)
- …multiple processing nodes, electrical testing, environmental and QCI screening, and failure analysis , the NGMC is a leader in designing, fabricating, packaging and ... all within a culture of design. We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The ideal… more
- SpaceX (Irvine, CA)
- …for test modes + Timing closure ownership throughout the entire project cycle ( RTL , synthesis, and physical implementation) + Analysis of clock domain crossing ... teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL +...Functional ECOs for complex blocks + Deploy and enhance methodology and flows related to timing constraint generation and… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... to evaluate the industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more