- Google (Sunnyvale, CA)
- …AXI) and scripting languages (ie Tcl, Python or Perl). + Experience in UPF for low-power design , including power intent specification, verification, and ... this role, you will join a team working on SoC -level RTL design for our data center...data paths. + Develop and maintain Unified Power Format ( UPF ) specifications for power management of the design… more
- Micron Technology, Inc. (Richardson, TX)
- …that are transforming how the world uses information to enrich life. As an HBM SOC Design and Integration Engineer , you will be responsible for the ... is successful. You will apply your deep understanding of SOC Architecture, RTL Logic Design , IP Integration,...performance and low power consumption and how to use UPF . + Good knowledge of static timing analysis, synthesis… more
- Micron Technology, Inc. (Richardson, TX)
- …technologies that are transforming how the world uses information to enrich life. As an HBM SOC Physical Design Engineer , you will be responsible for the ... is successful. You will apply your deep understanding of SOC Structural Design , high-speed interface design...Tools. + A solid understanding of Unified Power Format ( UPF ) for describing power intent. + Excellent knowledge of… more
- SpaceX (Irvine, CA)
- Sr. SOC /ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a future ... ultimate goal of enabling human life on Mars. SR. SOC /ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER ...and STA Signoff. + Experience with power intent and upf development for block and soc top.… more
- Belcan (Palo Alto, CA)
- Sr. Physical Design Engineer Job Number: 354330 Category: ...contribute to all design phases of physical design of high performance SoC design ... Design Engineering Description: Job Title: Sr. Physical Design Engineer Pay rate: $66.34 /hr. Location:...to GDSII. You will collaborate with the Foundry Process Engineer , SoC Architect, Microarchitecture, Packaging, Signal Integrity… more
- Meta (Austin, TX)
- …execution. 3. Deliver physical design of an end-to-end IP or integration of ASIC/ SoC design and point out lower power and higher performance trade-offs. 4. ... Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design … more
- Meta (Sunnyvale, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital ... our industry leading virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block… more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, from ... development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to… more
- Meta (Austin, TX)
- …SoCs that accelerate machine-learning and compute-vision workloads. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital ... Qualifications: 8. 3+ years of experience as a Hardware Design Engineer for production silicon shipped in...design uArchitecture and RTL coding 10. Experience in SoC bus and interconnect protocols 11. Experience with at… more
- Meta (Austin, TX)
- …execution. 3. Deliver physical design of an end-to-end IP or integration of ASIC/ SoC design and point out lower power and higher performance trade-offs. 4. ... Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design … more