- SpaceX (Irvine, CA)
- Sr . SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) at SpaceX Irvine, CA SpaceX was founded under the belief that a ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC TIMING ...COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer/ Senior : $170,000.00 - $230,000.00/per year Your actual level and… more
- SpaceX (Redmond, WA)
- Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Redmond, WA SpaceX was founded under the belief that a future where humanity is out ... to make this possible, with the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- Teradyne (North Reading, MA)
- …delivers better business results. Opportunity Overview Teradyne is seeking a Senior Principal Semiconductor Product Definer in the Silicon Strategy and Technology ... IP's roadmap and continual development in response to long-term market trends. T his senior role features extensive senior management exposure, and is a leading… more
- SpaceX (Irvine, CA)
- Sr . ASIC Design Engineer (Silicon Engineering) at... clean design + Participate in all phases of ASIC and/or FPGA design flow (eg synthesis, timing ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER (SILICON ENGINEERING) At...problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with… more
- Qualcomm (San Diego, CA)
- …entering new area such as the PC market. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills. Besides ASIC and/or FPGA ... This is a great opportunity to join a fast-paced SoC team responsible for RTL Design, flows and methodology...As new projects are coming up, making it wonderful timing to join our team. An ideal candidate will… more
- Amazon (San Diego, CA)
- …role you will: . Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets. . Define, ... configure and integration SoC Subsystems . Contribute to the SoC ...DFT on the blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention ... to design and implement the world's leading GPU and SoC 's. With the System- ASIC team, you will...be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Floorplan Design Engineer! NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world's ... leading SoC 's and GPU's. This position offers you a unique...timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical… more
- Capgemini (San Francisco, CA)
- …digital top level and/or blocks, with experience across the complete ASIC / SOC design flow including routing, static timing closure, EM/IR analysis and ... **Physical Design Engineer** **Job Description:** **The ASIC Physical Design Engineer will be responsible for taking ownership of the physical chip development,… more
- NVIDIA (WA)
- We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC 's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more