- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- US Tech Solutions (San Francisco, CA)
- …8 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... **Job Description:** + The project relates to the design and verification of a custom...in analog and real number modeling preferred **Skills:** + UVM (Universal Verification Methodology) + FPGA tools… more
- BAE Systems (San Diego, CA)
- …generating scripts (Perl, Tcl, Python, shell, etc.) + Working knowledge of UVM / SystemVerilog and familiarity with design verification + Working knowledge ... has an open position for a Senior FPGA Digital Design Engineer! See what you re missing. Our employees...+ Experience with designer-level test bench (VHDL, Verilog, or SystemVerilog ) + Familiarity with revision control (GIT, CVS, Clearcase,… more
- BAE Systems (Austin, TX)
- … team + Experience with high speed ADC/DAC interfaces + Experience with UVM / SystemVerilog and working with design verification teams + Working knowledge ... Description** BAE Systems is seeking a Senior Principal FPGA Design Engineer! See what you re missing. Our employees...Engineering Group is looking for a Senior Principal FPGA Design Engineer to support FPGA designs through all phases… more
- Google (Madison, WI)
- …verification methodology such as UVM /OVM/VMM. + Experience with the full verification life cycle. + Experience in SystemVerilog . + Excellent team player, ... new technologies. In this role, you will use your design and verification expertise to verify complex...+ Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology ( UVM… more
- Google (Mountain View, CA)
- …5 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... scenarios. + Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM ) or verify… more
- Meta (Sunnyvale, CA)
- …development cycles. 10. 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...practical experience. 8. 5+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (Sunnyvale, CA)
- … verification . 10. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- …in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience with Design verification of ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...development cycles 9. 15+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (Austin, TX)
- …ASIC development cycles 9. 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...to joining Meta. 7. 3+ years hands-on experience in SystemVerilog / UVM methodology or C/C++ based verification… more