- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- BAE Systems (Nashua, NH)
- …generating scripts (Perl, Tcl, Python, shell, etc.) + Working knowledge of UVM / SystemVerilog and familiarity with design verification + Working knowledge ... has an open position for a Principle FPGA Digital Design Engineer! See what you re missing. Our employees...+ Experience with designer-level test bench (VHDL, Verilog, or SystemVerilog ) + Familiarity with revision control (GIT, CVS, Clearcase,… more
- Skyworks (Cedar Rapids, IA)
- …Skills + BS & 5+ yrs (MS & 3+ yrs) experience in integrated circuit design / verification required + Expert in SystemVerilog and HDL programming languages + ... will include but not be limited to creating generalized SystemVerilog UVM testbenches with full functionality coverage...new verification tools to be used by verification / design teams + Work with design… more
- Google (Mountain View, CA)
- …5 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... scenarios. + Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM ) or verify… more
- Google (Madison, WI)
- …RTL using SystemVerilog for ASICs. Preferred qualifications: + Experience with verification methodology (eg, UVM /OVM/VMM). + Experience with the full ... and its integration within AI/ML-driven systems. As an ASIC Design Verification Engineer, you will use your...+ Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology ( UVM… more
- Meta (Salem, OR)
- … verification . 10. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Austin, TX)
- …in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience with Design verification of ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...development cycles 9. 14+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (Austin, TX)
- …ASIC development cycles 9. 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...to joining Meta. 7. 3+ years hands-on experience in SystemVerilog / UVM methodology or C/C++ based verification… more
- Meta (Sunnyvale, CA)
- …development cycles. 10. 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...practical experience. 8. 5+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (San Diego, CA)
- … UVM methodology. 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 10. Experience ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...13. Experience in development of UVM based verification environments from scratch. 14. Experience with Design… more