- Textron (Wilmington, MA)
- ** UVM Design Verification Engineer III** **Description** **_Who We Are_** Textron Systems is part of Textron, a $14 billion, multi\-industry company ... and ASIC designs for our electronic systems\. The FPGA/ASIC Design Verification Engineer will be...designs * Develop test benches for FPGA or ASIC design verification using UVM , System… more
- US Tech Solutions (Goleta, CA)
- …internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer , you will own functional verification ... **Job Description:** + The project relates to the design and verification of a custom...and testing. **Mandatory:** + 8 years of experience with verification methodologies and languages such as UVM … more
- US Tech Solutions (San Francisco, CA)
- **Job Description:** + The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as ... verification infrastructure to ensure functional correctness of a design as well as improve the throughput of the...and testing **Experience:** + 8 years of experience with verification methodologies and languages such as UVM … more
- L3Harris (Salt Lake City, UT)
- Job Title: Lead, FPGA UVM Design Engineer Job Location: Salt Lake City, UT Job Code: 18862 Work Schedule: 9x80 Job Description: We are looking for a talented ... FPGA design engineer with industry experience in Universal Verification Methodology ( UVM ), wireless digital communications, modems, networking, and/or… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will...responsible for the verification closure of a design module or sub-system from test-planning, UVM … more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will...responsible for the verification closure of a design module or sub-system from test-planning, UVM … more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will...SystemVerilog UVM /OVM based methodologies 11. Experience with Design verification of Data-center applications like Video,… more
- Meta (Austin, TX)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will...responsible for the verification closure of a design module or sub-system from test-planning, UVM … more
- SpaceX (Sunnyvale, CA)
- Design Verification Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX was founded under the belief that a future where humanity is out exploring ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)...in electrical engineering or computer engineering + Experience with verification methodologies such as UVM + Strong… more
- Meta (Austin, TX)
- …the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work ... for multiple state of the art IPs. **Required Skills:** Design Verification Engineer Responsibilities: 1....14. Experience in development of UVM based verification environments from scratch. 15. Experience with Design… more